Master of Science in VLSI Design and Embedded Systems

This course** provides learners with the foundational knowledge and applied skills essential for careers in the semiconductor and embedded systems industry. The course integrates theoretical concepts with practical implementation, covering both front-end and back-end VLSI design methodologies. Learners are introduced to VLSI design principles, ASIC and FPGA workflows, and industry-standard verification processes. Building on digital logic fundamentals, the course incorporates the RISC-V Instruction Set Architecture, guiding students toward the Register Transfer Level (RTL) design and implementation of a pipelined RISC-V processor. In addition, learners explore CMOS basics, full-custom ASIC design strategies, and critical timing concepts. By connecting digital electronics theory with practical applications, the course enables students to design systems that are functionally correct, synthesizable, and optimized for performance and resource efficiency.

This course provides a structured introduction to the Verilog Hardware Description Language (HDL), equipping learners with the ability to model, simulate, and design digital systems at the RTL level. The course begins with the fundamentals of Verilog, including modules, data types, procedural and continuous assignments, as well as behavioral and structural modeling. Learners will gain practical experience in hardware design environments through the use of Linux commands and the VI editor. Building on this foundation, the course advances to complex Verilog concepts such as tasks, functions, synthesizable constructs, and testbench development, with a strong emphasis on writing modular, reusable, and efficient code. Finally, learners are introduced to code coverage techniques, enabling them to evaluate verification quality and completeness effectively.

This course lays the foundation for developing and debugging modern embedded systems. The course begins with hardware system interfacing fundamentals and introduces learners to microprocessors and microcontrollers, with platforms such as STMicroelectronics serving as examples. Emphasis is placed on embedded C programming for system-level applications. Learners also gain exposure to the ARM Instruction Set Architecture (ISA) and supporting toolchains, while exploring key quality attributes of embedded systems. Additionally, the course introduces debug interfaces and debuggers such as SWD and JTAG, providing practical insight into low-level programming, system control, and debugging practices essential for embedded system development.

This course builds on foundational concepts to provide learners with a comprehensive understanding of embedded peripheral interfaces from a programmer’s perspective. The course explores the internal functionality and software-level integration of analog and digital peripherals, such as ADCs, DACs, sensors, buttons, LEDs, LCDs, and other input/output devices, using microcontroller platforms. Learners will gain practical experience in controlling and interfacing peripherals through embedded programming.

In addition, the course introduces the fundamentals of embedded networking, covering widely used communication stacks and protocols including TCP/IP and UDP. Emphasis is placed on the layered architecture of networking stacks, packet structures, socket programming, and applications in IoT and embedded systems. Through applied programming exercises and lab-based activities, learners will acquire hands-on skills in peripheral integration and implementing network communication protocols for real-world embedded applications.

This course introduces learners to the architecture, design methodologies, and communication protocols central to modern System-on-Chip (SoC) development. The course begins with a detailed study of SoC architecture, emphasizing the integration of processing cores, memory subsystems, and hardware accelerators. Learners will gain an understanding of the complete SoC design flow, including specification, IP integration, simulation, synthesis, verification, and physical design. The course highlights interconnect protocols such as AXI, AHB, and APB, exploring how bridges and bus fabrics enable seamless communication between IP blocks. Additionally, students will examine processor–peripheral communication through protocols like I²C, SPI, UART, and GPIO, while also being introduced to wireless communication standards such as Wi-Fi and Bluetooth. Special focus is placed on their architectures, stack layers, and the integration challenges encountered in SoC design.

This course introduces learners to the fundamental and performance-driven principles of modern computer systems. The course begins with an exploration of processor instruction set architectures (ISAs), covering both RISC and CISC paradigms, as well as system-level models such as Von Neumann and Harvard architectures. Learners study essential components, including address, data, and control buses, interrupt controllers, and Direct Memory Access (DMA), alongside the fundamentals of memory organization. The course then covers virtual memory concepts such as address translation, page tables, and Translation Lookaside Buffers (TLBs). Building on this foundation, learners engage with high-performance design techniques, including instruction pipelining, address pipelining, and parallel processing. A dedicated unit on cache architecture provides an in-depth understanding of the memory hierarchy, cache mapping methods, replacement and write policies, and coherence protocols, including an introduction to the Cache Coherent Interconnect for Accelerators (CHI). By connecting theory with real-world processor design practices, the course equips students with insights into how modern systems achieve efficiency, scalability, and performance.

This course offers an advanced study of the RISC-V architecture, with a focus on system-level design and specialized extensions. Learners will develop a detailed understanding of privilege modes, memory protection, exception and interrupt handling, and system programming within RISC-V. Emphasis is placed on practical engagement with RISC-V toolchains, debugging methods, and application development for both embedded and general-purpose platforms. The course also introduces key ISA specifications such as PLIC, Debug, and Trace, alongside support for extensions including vector, atomic, floating-point, bit manipulation, and custom ISAs. By the end of the course, students will be equipped to leverage the flexibility of the open RISC-V ecosystem to design high-performance and domain-specific applications. This course also explores contemporary processor architectures with emphasis on hardware virtualisation support, throughput-oriented GPU designs, and heterogeneous computing paradigms. Learners critically evaluate hypervisor-aware architectures, GPU scheduling mechanisms, and advanced memory hierarchies using real-world architectural examples.

This course provides an in-depth exploration of advanced embedded system design, integrating both hardware and software perspectives. Learners will engage with embedded Linux programming, real-time operating system concepts, and security mechanisms for modern embedded platforms. The course introduces advanced processor architectures, hardware/software co-design methodologies, and parallel computing techniques to support the development of efficient, secure, and high-performance solutions. Practical application is emphasized through Linux-based environments and FPGA-based implementations, enabling learners to connect theoretical foundations with real-world embedded system applications.

This course provides learners with the expertise to design and implement intelligent embedded solutions for edge and IoT environments. Starting with core principles of IoT and embedded machine learning, students advance to understanding industrial communication protocols, edge device orchestration, and secure data management. The curriculum emphasizes real-time AI inferencing, optimization of embedded models, and applications of generative AI in IoT and SoC workflows. With a strong hands-on approach, the course prepares engineers to create secure, scalable, and high-performance AI-driven embedded systems for edge computing.

This course emphasizes the application of embedded systems across specialized domains such as robotics, automotive, healthcare, and RF technologies. Learners will engage with advanced topics including autonomous navigation for robotic platforms, RFIC and PCB-based system design, and the development of medical-grade embedded devices aligned with regulatory standards. The curriculum integrates advanced perception, signal integrity, cryptographic security, and system assurance to support the creation of robust, domain-specific embedded applications. Through real-world case studies and practical projects, students gain the expertise to address industry challenges and drive innovation in embedded product design and deployment. The course also explores embedded system design for AI-enabled applications, focusing on integration of NPUs and accelerator-centric processing pipelines. Learners evaluate accelerator dataflows, memory hierarchies, and HW–SW coordination in real-time embedded AI systems.

This course offers an in-depth introduction to the hardware foundations of modern electronics, focusing on Printed Circuit Board (PCB) design, semiconductor device physics, and wafer manufacturing processes. Learners will gain insights into PCB design workflows, including schematic capture, component placement, routing, and design rule checks, with particular attention to signal integrity and manufacturability. The course also examines the behavior and modeling of essential semiconductor devices such as diodes, BJTs, and MOSFETs, which underpin both analog and digital circuit design. Furthermore, it introduces the semiconductor fabrication process, covering wafer preparation, photolithography, doping, etching, and packaging techniques. By integrating these perspectives, students will develop a foundational understanding of how electronic systems are designed and realized—from raw silicon to complete board-level implementation.

This course provides a comprehensive exploration of the post-silicon phase of semiconductor development, emphasizing Packaging Design, Package Assembly, and IC Testing. Learners will examine the principles and design methodologies used in semiconductor packaging, with a focus on optimizing thermal, mechanical, and electrical performance. The course further introduces key assembly processes, including die attach, wire bonding, flip-chip technology, and encapsulation, highlighting issues of reliability and manufacturability. In addition, students will study integrated circuit (IC) testing approaches, such as wafer-level and package-level testing, test coverage evaluation, and defect detection methods. By integrating these elements, the course equips learners with the expertise to connect silicon fabrication with system-level deployment, ensuring robust and reliable chip production.

This course provides learners with a deep understanding of emerging innovations in System-on-Chip architectures, with a particular focus on multi-die and chiplet-based systems. The course begins with an overview of Systems of Chips, chiplets, and advanced integration techniques, emphasizing the industry transition from monolithic designs to modular and scalable architectures. A central theme is the Universal Chiplet Interconnect Express (UCIe), a new standard enabling seamless, high-bandwidth die-to-die communication across heterogeneous components. Learners will also engage with a case study on RISC-V SoC design, exploring open-source hardware concepts, subsystem integration, and real-world design flows. This applied component reinforces architectural principles while highlighting practical industry practices. By the end of the course, students will be equipped with advanced knowledge of SoC design concepts, interconnect protocols, and multi-die integration strategies, preparing them for roles in silicon design, system architecture, and semiconductor product development. This course also focuses on advanced SoC architectures incorporating hardware virtualisation, AI accelerators, and hardware–software co-design methodologies. Learners design and evaluate simplified accelerator blocks within SoC pipelines, analysing performance, memory access, and HW–SW interaction for AI workloads.

This course provides an in-depth study of front-end design challenges and solutions in advanced digital systems, with emphasis on Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), low-power design methodologies, and RTL signoff techniques. Learners will explore methods to identify and resolve CDC and RDC issues for robust data transfer across asynchronous domains. The course also examines low-power design strategies, such as clock gating, power gating, multi-voltage operation, and UPF-based power intent specification. In addition, students will gain hands-on experience with RTL linting, logic synthesis, and formal equivalence checking, ensuring that RTL designs are functionally accurate, optimized, and ready for physical implementation. Through a mix of theoretical concepts and tool-driven labs, learners will build the ability to address design quality, power efficiency, and correctness in complex SoC and ASIC development.

This course offers an in-depth exploration of FPGA-based digital system design, starting with the fundamentals and progressing to advanced implementation techniques. Learners will study FPGA architectures, design flows, and hardware description languages (Verilog/VHDL) to model and realize digital circuits on reconfigurable hardware. The curriculum extends to advanced topics such as IP integration, high-speed interfaces, clocking strategies, and design optimization with respect to performance, power, and area. Students will also engage with specialized FPGA features, including embedded processors, DSP blocks, and high-level synthesis (HLS) for design acceleration. Through hands-on labs and project-based activities, participants will acquire practical expertise in developing, verifying, and deploying complex FPGA-based designs, preparing them for applications in prototyping, embedded systems, and hardware acceleration.

This course provides a comprehensive study of Analog and Mixed-Signal (AMS) Integrated Circuit (IC) Design, combining theoretical foundations with advanced design and verification methodologies. Beginning with core circuit theory to establish analytical rigor, students will design essential analog building blocks such as current mirrors, differential amplifiers, and operational amplifiers. The course advances into specialized topics including biasing strategies, frequency compensation, noise analysis, and low-power/low-voltage design techniques. Learners will also develop expertise in AMS behavioral modeling and verification, applying high-level abstractions to model analog behavior and validate mixed-signal systems. Through a blend of theoretical analysis, simulations, and project-based labs, students will gain the ability to design, analyze, and verify complex AMS circuits, preparing them for applications in communication, sensing, and power management systems.

This module also addresses advanced digital design techniques for high-throughput computing, including GPU-inspired parallel architectures. Students analyse SIMT processing elements, warp scheduling concepts, and throughput-driven VLSI design strategies through design-oriented exercises.

This course introduces students to advanced verification and debugging techniques within the digital design flow, with a particular emphasis on Gate-Level Simulation (GLS) and the Universal Verification Methodology (UVM). Learners will explore the role of GLS in validating post-synthesis and post-place-and-route netlists, focusing on critical issues such as timing accuracy, glitches, and X-propagation. The course further provides a comprehensive overview of UVM, an industry-standard framework for developing reusable, modular, and scalable verification environments in SystemVerilog. Key topics include transaction-level modeling, sequences, drivers, monitors, and scoreboards, along with portable stimulus generation demonstrated through a case study. Through practical labs and simulation-based exercises, students will gain hands-on experience in debugging gate-level designs and constructing structured verification environments for complex SoC implementations.

This course delves into power-aware verification methodologies that are crucial for developing modern, energy-efficient integrated circuits. With power efficiency now a key requirement in applications such as mobile devices and IoT systems, this course emphasizes the importance of verifying low-power intent across different stages of the design cycle. Learners will study the IEEE 1801 Unified Power Format (UPF), which defines power management intent separately from RTL design. Key topics include the fundamentals of UPF-based design and verification—covering power domain creation, isolation techniques, level shifting, retention mechanisms, and power state tables. The course also highlights how UPF integrates into simulation and verification workflows to accurately model power intent and detect functional issues such as missing retention or faulty isolation. Through guided labs and hands-on exercises, participants will learn to set up UPF verification environments, conduct power-aware checks, and validate designs under various power conditions. By the end of the course, students will be equipped to analyze, detect, and resolve low-power design issues, ensuring functional correctness in complex, low-energy VLSI systems.

This course offers an in-depth study of digital design implementation and testing methodologies, blending theoretical concepts with practical training on industry-standard Synopsys tools. It begins with RTL linting to detect coding errors, design rule violations, and structural issues early in the design cycle. Students will then perform RTL synthesis, applying design constraints and incremental optimizations following DFT (Design for Test) insertion. The course also emphasizes formal equivalence checking to ensure functional correctness between RTL and synthesized netlists. In the testing domain, learners will study and apply advanced techniques such as LBIST (Logic Built-In Self-Test), MBIST (Memory Built-In Self-Test), and test compression methods to enhance in-system testing efficiency and reduce test overhead. Through guided labs, students will gain hands-on experience in preparing robust, testable, and silicon-ready designs.

This course delves into advanced Design-for-Testability (DFT) strategies tailored for low-power and complex SoC architectures. It emphasizes power-aware testing techniques to address challenges such as multi-power domains, power gating, and clock gating, ensuring efficient testability while maintaining high fault coverage. The course also introduces the IEEE 1687 (IJTAG) standard, which provides a scalable approach to accessing embedded instruments within SoC IP blocks. Students will gain hands-on experience in integrating IJTAG into SoC test infrastructures, enabling modular and reusable test solutions. Through a blend of theory and practical labs, learners will develop the ability to implement robust, power-aware, and standards-compliant DFT methodologies for modern SoC designs.

This course provides an in-depth understanding of advanced Static Timing Analysis (STA) and Physical Verification processes essential for ensuring both the functional accuracy and physical integrity of digital IC designs. Learners will study advanced STA concepts, including multi-mode multi-corner (MMMC) analysis, timing exceptions, clock domain crossing (CDC) verification, and techniques for managing on-chip variation (OCV). The course further explores critical Physical Verification steps such as Design Rule Checking (DRC), Layout Versus Schematic (LVS), Antenna Rule checks, and Electrostatic Discharge (ESD) compliance, leading to complete sign-off readiness. Emphasis is placed on applying industry-standard methodologies and EDA tool flows for achieving timing closure and manufacturability. Hands-on labs and case studies provide practical exposure to timing closure strategies, physical verification, and sign-off preparation, enabling students to confidently prepare designs for successful tape-out.

This course delves into advanced practices in digital IC implementation, with emphasis on power-aware physical design, AI-driven optimization, logic equivalence checking, and signal integrity analysis. Students will study methods to reduce both dynamic and static power during placement, routing, and clock tree synthesis, while integrating power intent specifications and multi-voltage domain design. The curriculum also highlights emerging AI/ML-based approaches for placement, congestion prediction, and timing closure, improving both productivity and design quality. A dedicated module on logic equivalence checking ensures functional alignment across design stages, from RTL through gate-level representations. Furthermore, learners will investigate signal integrity challenges such as crosstalk, noise, and delay variations, and apply corrective measures during physical design. Through hands-on labs and real-world case studies, students will acquire practical expertise in building high-performance, low-power chips using modern, intelligent design methodologies.

This course offers an in-depth study of two major processor architectures: ARM and RISC-V. It begins with the core principles of reduced instruction set computing (RISC), providing students with a solid understanding of their architectural foundations, instruction sets, and pipeline structures. Learners will then explore ARM-specific features, including software interfaces, exception handling, and peripheral programming, reinforced through practical coding exercises. The course advances into topics such as ARM TrustZone, memory protection units, and performance monitoring, highlighting security and optimization techniques. Alongside, comparative discussions of ARM and RISC-V design philosophies and ecosystem support prepare learners for embedded system development and System-on-Chip (SoC)-level integration using both architectures. This module also introduces advanced architectural features including low-level hardware virtualisation mechanisms, GPU execution models, and vector processing extensions. Students analyse MMU/IOMMU support, SIMT-based GPU architectures, and RISC-V Vector Extensions through comparative architectural case studies.

This course equips learners with the scripting and version control skills essential for streamlining modern VLSI design workflows. Beginning with Shell and TCL scripting, students learn to automate repetitive tasks and manage tool operations in electronic design automation (EDA) environments. These foundations are extended through Perl and Python, widely used in chip design for tasks such as data parsing, building automation frameworks, and handling large datasets. The course also introduces GitLab for source code management and collaborative development. Learners gain practical experience with version control systems, branching strategies, and workflow integration to manage design changes effectively within team-based projects. Through hands-on exercises and applied projects, students develop the ability to create robust automation scripts, optimize verification and implementation flows, and embed design processes into collaborative environments. The course is tailored for those seeking to accelerate chip development cycles and enhance productivity through intelligent automation. This module also examines modern design automation workflows, including AI-assisted EDA techniques for VLSI and embedded systems. Students evaluate how machine-learning-driven optimisation and NPU-aware design flows enhance synthesis, verification, and physical design efficiency.

This course provides a thorough introduction to Design for Testability (DFT) techniques essential in modern VLSI design for ensuring manufacturability and achieving high fault coverage. Learners will study fundamental concepts such as Automatic Test Pattern Generation (ATPG), fault models (stuck-at, transition, bridging), scan chain insertion, test compression, boundary scan (IEEE 1149.1), and test coverage analysis. The course integrates both theoretical foundations and hands-on practice, allowing students to implement and verify test structures through lab-based exercises. By the end of the course, learners will be equipped with the knowledge and skills to design circuits for testability, evaluate coverage metrics, and apply industry-standard DFT methodologies to practical silicon design challenges.

This course offers an in-depth exploration of SystemVerilog (SV) for both RTL design and functional verification, building a strong link between hardware description and validation. The course begins with RTL design using SystemVerilog, emphasizing synthesizable constructs, hierarchical design, and best practices for writing modular and reusable code. It then shifts focus to SystemVerilog as a Hardware Verification Language (HVL), introducing advanced verification techniques such as object-oriented programming, constrained randomization, and functional coverage. Learners will also gain proficiency in writing SystemVerilog Assertions (SVA) for property checking and applying formal verification to ensure design correctness early in the development cycle. Combining theoretical insights with hands-on practice, this course equips students with the ability to design reliable hardware and build efficient, assertion-based verification environments.

This course offers immersive, project-based practice in VLSI and embedded systems, allowing students to translate theoretical knowledge into real-world design and verification tasks. Learners gain proficiency with industry-standard tools, scripting workflows, and complete design methodologies. By engaging with practical exercises across multiple domains, students build the applied expertise and confidence required for careers in the semiconductor and embedded systems industries.

This course offers a comprehensive study of Physical Synthesis and Physical Design in the VLSI implementation flow, emphasizing the transformation of synthesized RTL into optimized and manufacturable layouts. Students will explore timing-driven placement, logic restructuring, and multi-objective optimization for area, power, and performance. The course further examines the complete Physical Design flow, covering floorplanning, placement, clock tree synthesis (CTS), routing, and signoff checks such as timing analysis. Through practical labs and industry-standard tool exercises, learners will develop the ability to perform both block-level and full-chip physical design, ensuring compliance with stringent fabrication and performance requirements.

This course provides an applied, integrative experience across semiconductor and embedded system design, bridging theory with real-world practice. Students engage in structured projects that involve design tool flows, scripting, verification, and testing strategies. Working through sub-block or full-chip development cycles with guided mentorship, learners participate in milestone-based reviews and collaborative problem-solving. This experience cultivates a comprehensive understanding of how multiple disciplines converge in chip design and production, preparing students for professional engineering environments.

This course provides an in-depth exploration of essential infrastructure components and software foundations in modern System-on-Chip (SoC) design. The course begins with a detailed study of memories and memory controllers, covering SRAM, DRAM, and Flash, along with interfacing methods and controller architectures designed to optimize latency, bandwidth, and power consumption. Learners will then examine Memory Management Units (MMUs) and virtual memory mechanisms such as address translation, paging, segmentation, and protection, which are integral to contemporary processor architectures. The course also focuses on interrupt controllers, exploring interrupt types, prioritization, masking, nested interrupts, and their integration with CPU cores to ensure responsive system performance. A dedicated section addresses SoC system controllers, including subsystems for clock and reset management, timers, power management units (PMUs), and pin multiplexing. Finally, the course introduces the SoC software stack, encompassing operating systems, firmware, device drivers, communication stacks, applications, and development toolchains. Through this, learners gain insights into the interplay between hardware and software, and how abstraction layers like firmware and drivers manage hardware resources effectively. ​​The module extends system-on-chip design concepts to include hardware virtualisation support and AI-oriented accelerator integration. Students examine virtualised SoC interconnects, NPU dataflows, and RISC-V vector capabilities within modern heterogeneous SoC architectures.

This course serves as the culminating experience in the VLSI and Embedded Systems program, designed to replicate real-world industry challenges while showcasing learners’ ability to deliver production-ready solutions. Students address complex, open-ended engineering problems that require the integration of advanced technical expertise, innovative thinking, and effective project management. Through the complete development cycle—from ideation and architectural design to detailed implementation, verification, optimization, and deployment—learners gain hands-on experience in building robust systems. Projects may focus on domains such as VLSI RTL design and verification, embedded systems for IoT, low-power digital architectures, FPGA-based accelerators, or intelligent embedded applications. Throughout the course, students collaborate in teams, maintain structured documentation, adhere to professional and industry standards, and present their outcomes through functional prototypes and technical presentations. The Capstone Project directly supports the programme’s aims by requiring students to integrate advanced technical knowledge, applied research methods, professional judgement, ethical responsibility, and autonomous project management in the delivery of a complex VLSI or embedded systems solution.

This course offers an advanced study of the RISC-V architecture, with a focus on system-level design and specialized extensions. Learners will develop a detailed understanding of privilege modes, memory protection, exception and interrupt handling, and system programming within RISC-V. Emphasis is placed on practical engagement with RISC-V toolchains, debugging methods, and application development for both embedded and general-purpose platforms. The course also introduces key ISA specifications such as PLIC, Debug, and Trace, alongside support for extensions including vector, atomic, floating-point, bit manipulation, and custom ISAs. By the end of the course, students will be equipped to leverage the flexibility of the open RISC-V ecosystem to design high-performance and domain-specific applications. This course also explores contemporary processor architectures with emphasis on hardware virtualisation support, throughput-oriented GPU designs, and heterogeneous computing paradigms. Learners critically evaluate hypervisor-aware architectures, GPU scheduling mechanisms, and advanced memory hierarchies using real-world architectural examples.

This course provides an in-depth exploration of advanced embedded system design, integrating both hardware and software perspectives. Learners will engage with embedded Linux programming, real-time operating system concepts, and security mechanisms for modern embedded platforms. The course introduces advanced processor architectures, hardware/software co-design methodologies, and parallel computing techniques to support the development of efficient, secure, and high-performance solutions. Practical application is emphasized through Linux-based environments and FPGA-based implementations, enabling learners to connect theoretical foundations with real-world embedded system applications.

This course provides learners with the expertise to design and implement intelligent embedded solutions for edge and IoT environments. Starting with core principles of IoT and embedded machine learning, students advance to understanding industrial communication protocols, edge device orchestration, and secure data management. The curriculum emphasizes real-time AI inferencing, optimization of embedded models, and applications of generative AI in IoT and SoC workflows. With a strong hands-on approach, the course prepares engineers to create secure, scalable, and high-performance AI-driven embedded systems for edge computing.

This course emphasizes the application of embedded systems across specialized domains such as robotics, automotive, healthcare, and RF technologies. Learners will engage with advanced topics including autonomous navigation for robotic platforms, RFIC and PCB-based system design, and the development of medical-grade embedded devices aligned with regulatory standards. The curriculum integrates advanced perception, signal integrity, cryptographic security, and system assurance to support the creation of robust, domain-specific embedded applications. Through real-world case studies and practical projects, students gain the expertise to address industry challenges and drive innovation in embedded product design and deployment. The course also explores embedded system design for AI-enabled applications, focusing on integration of NPUs and accelerator-centric processing pipelines. Learners evaluate accelerator dataflows, memory hierarchies, and HW–SW coordination in real-time embedded AI systems.

This course offers an in-depth introduction to the hardware foundations of modern electronics, focusing on Printed Circuit Board (PCB) design, semiconductor device physics, and wafer manufacturing processes. Learners will gain insights into PCB design workflows, including schematic capture, component placement, routing, and design rule checks, with particular attention to signal integrity and manufacturability. The course also examines the behavior and modeling of essential semiconductor devices such as diodes, BJTs, and MOSFETs, which underpin both analog and digital circuit design. Furthermore, it introduces the semiconductor fabrication process, covering wafer preparation, photolithography, doping, etching, and packaging techniques. By integrating these perspectives, students will develop a foundational understanding of how electronic systems are designed and realized—from raw silicon to complete board-level implementation.

This course provides a comprehensive exploration of the post-silicon phase of semiconductor development, emphasizing Packaging Design, Package Assembly, and IC Testing. Learners will examine the principles and design methodologies used in semiconductor packaging, with a focus on optimizing thermal, mechanical, and electrical performance. The course further introduces key assembly processes, including die attach, wire bonding, flip-chip technology, and encapsulation, highlighting issues of reliability and manufacturability. In addition, students will study integrated circuit (IC) testing approaches, such as wafer-level and package-level testing, test coverage evaluation, and defect detection methods. By integrating these elements, the course equips learners with the expertise to connect silicon fabrication with system-level deployment, ensuring robust and reliable chip production.

This course provides learners with a deep understanding of emerging innovations in System-on-Chip architectures, with a particular focus on multi-die and chiplet-based systems. The course begins with an overview of Systems of Chips, chiplets, and advanced integration techniques, emphasizing the industry transition from monolithic designs to modular and scalable architectures. A central theme is the Universal Chiplet Interconnect Express (UCIe), a new standard enabling seamless, high-bandwidth die-to-die communication across heterogeneous components. Learners will also engage with a case study on RISC-V SoC design, exploring open-source hardware concepts, subsystem integration, and real-world design flows. This applied component reinforces architectural principles while highlighting practical industry practices. By the end of the course, students will be equipped with advanced knowledge of SoC design concepts, interconnect protocols, and multi-die integration strategies, preparing them for roles in silicon design, system architecture, and semiconductor product development. This course also focuses on advanced SoC architectures incorporating hardware virtualisation, AI accelerators, and hardware–software co-design methodologies. Learners design and evaluate simplified accelerator blocks within SoC pipelines, analysing performance, memory access, and HW–SW interaction for AI workloads.

This course provides an in-depth study of front-end design challenges and solutions in advanced digital systems, with emphasis on Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), low-power design methodologies, and RTL signoff techniques. Learners will explore methods to identify and resolve CDC and RDC issues for robust data transfer across asynchronous domains. The course also examines low-power design strategies, such as clock gating, power gating, multi-voltage operation, and UPF-based power intent specification. In addition, students will gain hands-on experience with RTL linting, logic synthesis, and formal equivalence checking, ensuring that RTL designs are functionally accurate, optimized, and ready for physical implementation. Through a mix of theoretical concepts and tool-driven labs, learners will build the ability to address design quality, power efficiency, and correctness in complex SoC and ASIC development.

This course offers an in-depth exploration of FPGA-based digital system design, starting with the fundamentals and progressing to advanced implementation techniques. Learners will study FPGA architectures, design flows, and hardware description languages (Verilog/VHDL) to model and realize digital circuits on reconfigurable hardware. The curriculum extends to advanced topics such as IP integration, high-speed interfaces, clocking strategies, and design optimization with respect to performance, power, and area. Students will also engage with specialized FPGA features, including embedded processors, DSP blocks, and high-level synthesis (HLS) for design acceleration. Through hands-on labs and project-based activities, participants will acquire practical expertise in developing, verifying, and deploying complex FPGA-based designs, preparing them for applications in prototyping, embedded systems, and hardware acceleration.

This course provides a comprehensive study of Analog and Mixed-Signal (AMS) Integrated Circuit (IC) Design, combining theoretical foundations with advanced design and verification methodologies. Beginning with core circuit theory to establish analytical rigor, students will design essential analog building blocks such as current mirrors, differential amplifiers, and operational amplifiers. The course advances into specialized topics including biasing strategies, frequency compensation, noise analysis, and low-power/low-voltage design techniques. Learners will also develop expertise in AMS behavioral modeling and verification, applying high-level abstractions to model analog behavior and validate mixed-signal systems. Through a blend of theoretical analysis, simulations, and project-based labs, students will gain the ability to design, analyze, and verify complex AMS circuits, preparing them for applications in communication, sensing, and power management systems.

This module also addresses advanced digital design techniques for high-throughput computing, including GPU-inspired parallel architectures. Students analyse SIMT processing elements, warp scheduling concepts, and throughput-driven VLSI design strategies through design-oriented exercises.

This course introduces students to advanced verification and debugging techniques within the digital design flow, with a particular emphasis on Gate-Level Simulation (GLS) and the Universal Verification Methodology (UVM). Learners will explore the role of GLS in validating post-synthesis and post-place-and-route netlists, focusing on critical issues such as timing accuracy, glitches, and X-propagation. The course further provides a comprehensive overview of UVM, an industry-standard framework for developing reusable, modular, and scalable verification environments in SystemVerilog. Key topics include transaction-level modeling, sequences, drivers, monitors, and scoreboards, along with portable stimulus generation demonstrated through a case study. Through practical labs and simulation-based exercises, students will gain hands-on experience in debugging gate-level designs and constructing structured verification environments for complex SoC implementations.

This course delves into power-aware verification methodologies that are crucial for developing modern, energy-efficient integrated circuits. With power efficiency now a key requirement in applications such as mobile devices and IoT systems, this course emphasizes the importance of verifying low-power intent across different stages of the design cycle. Learners will study the IEEE 1801 Unified Power Format (UPF), which defines power management intent separately from RTL design. Key topics include the fundamentals of UPF-based design and verification—covering power domain creation, isolation techniques, level shifting, retention mechanisms, and power state tables. The course also highlights how UPF integrates into simulation and verification workflows to accurately model power intent and detect functional issues such as missing retention or faulty isolation. Through guided labs and hands-on exercises, participants will learn to set up UPF verification environments, conduct power-aware checks, and validate designs under various power conditions. By the end of the course, students will be equipped to analyze, detect, and resolve low-power design issues, ensuring functional correctness in complex, low-energy VLSI systems.

This course offers an in-depth study of digital design implementation and testing methodologies, blending theoretical concepts with practical training on industry-standard Synopsys tools. It begins with RTL linting to detect coding errors, design rule violations, and structural issues early in the design cycle. Students will then perform RTL synthesis, applying design constraints and incremental optimizations following DFT (Design for Test) insertion. The course also emphasizes formal equivalence checking to ensure functional correctness between RTL and synthesized netlists. In the testing domain, learners will study and apply advanced techniques such as LBIST (Logic Built-In Self-Test), MBIST (Memory Built-In Self-Test), and test compression methods to enhance in-system testing efficiency and reduce test overhead. Through guided labs, students will gain hands-on experience in preparing robust, testable, and silicon-ready designs.

This course delves into advanced Design-for-Testability (DFT) strategies tailored for low-power and complex SoC architectures. It emphasizes power-aware testing techniques to address challenges such as multi-power domains, power gating, and clock gating, ensuring efficient testability while maintaining high fault coverage. The course also introduces the IEEE 1687 (IJTAG) standard, which provides a scalable approach to accessing embedded instruments within SoC IP blocks. Students will gain hands-on experience in integrating IJTAG into SoC test infrastructures, enabling modular and reusable test solutions. Through a blend of theory and practical labs, learners will develop the ability to implement robust, power-aware, and standards-compliant DFT methodologies for modern SoC designs.

This course provides an in-depth understanding of advanced Static Timing Analysis (STA) and Physical Verification processes essential for ensuring both the functional accuracy and physical integrity of digital IC designs. Learners will study advanced STA concepts, including multi-mode multi-corner (MMMC) analysis, timing exceptions, clock domain crossing (CDC) verification, and techniques for managing on-chip variation (OCV). The course further explores critical Physical Verification steps such as Design Rule Checking (DRC), Layout Versus Schematic (LVS), Antenna Rule checks, and Electrostatic Discharge (ESD) compliance, leading to complete sign-off readiness. Emphasis is placed on applying industry-standard methodologies and EDA tool flows for achieving timing closure and manufacturability. Hands-on labs and case studies provide practical exposure to timing closure strategies, physical verification, and sign-off preparation, enabling students to confidently prepare designs for successful tape-out.

This course delves into advanced practices in digital IC implementation, with emphasis on power-aware physical design, AI-driven optimization, logic equivalence checking, and signal integrity analysis. Students will study methods to reduce both dynamic and static power during placement, routing, and clock tree synthesis, while integrating power intent specifications and multi-voltage domain design. The curriculum also highlights emerging AI/ML-based approaches for placement, congestion prediction, and timing closure, improving both productivity and design quality. A dedicated module on logic equivalence checking ensures functional alignment across design stages, from RTL through gate-level representations. Furthermore, learners will investigate signal integrity challenges such as crosstalk, noise, and delay variations, and apply corrective measures during physical design. Through hands-on labs and real-world case studies, students will acquire practical expertise in building high-performance, low-power chips using modern, intelligent design methodologies.

This course introduces learners to the fundamental and performance-driven principles of modern computer systems. The course begins with an exploration of processor instruction set architectures (ISAs), covering both RISC and CISC paradigms, as well as system-level models such as Von Neumann and Harvard architectures. Learners study essential components, including address, data, and control buses, interrupt controllers, and Direct Memory Access (DMA), alongside the fundamentals of memory organization. The course then covers virtual memory concepts such as address translation, page tables, and Translation Lookaside Buffers (TLBs). Building on this foundation, learners engage with high-performance design techniques, including instruction pipelining, address pipelining, and parallel processing. A dedicated unit on cache architecture provides an in-depth understanding of the memory hierarchy, cache mapping methods, replacement and write policies, and coherence protocols, including an introduction to the Cache Coherent Interconnect for Accelerators (CHI). By connecting theory with real-world processor design practices, the course equips students with insights into how modern systems achieve efficiency, scalability, and performance.

This course offers an in-depth study of two major processor architectures: ARM and RISC-V. It begins with the core principles of reduced instruction set computing (RISC), providing students with a solid understanding of their architectural foundations, instruction sets, and pipeline structures. Learners will then explore ARM-specific features, including software interfaces, exception handling, and peripheral programming, reinforced through practical coding exercises. The course advances into topics such as ARM TrustZone, memory protection units, and performance monitoring, highlighting security and optimization techniques. Alongside, comparative discussions of ARM and RISC-V design philosophies and ecosystem support prepare learners for embedded system development and System-on-Chip (SoC)-level integration using both architectures. This module also introduces advanced architectural features including low-level hardware virtualisation mechanisms, GPU execution models, and vector processing extensions. Students analyse MMU/IOMMU support, SIMT-based GPU architectures, and RISC-V Vector Extensions through comparative architectural case studies.

This course equips learners with the scripting and version control skills essential for streamlining modern VLSI design workflows. Beginning with Shell and TCL scripting, students learn to automate repetitive tasks and manage tool operations in electronic design automation (EDA) environments. These foundations are extended through Perl and Python, widely used in chip design for tasks such as data parsing, building automation frameworks, and handling large datasets. The course also introduces GitLab for source code management and collaborative development. Learners gain practical experience with version control systems, branching strategies, and workflow integration to manage design changes effectively within team-based projects. Through hands-on exercises and applied projects, students develop the ability to create robust automation scripts, optimize verification and implementation flows, and embed design processes into collaborative environments. The course is tailored for those seeking to accelerate chip development cycles and enhance productivity through intelligent automation. This module also examines modern design automation workflows, including AI-assisted EDA techniques for VLSI and embedded systems. Students evaluate how machine-learning-driven optimisation and NPU-aware design flows enhance synthesis, verification, and physical design efficiency.

This course provides a thorough introduction to Design for Testability (DFT) techniques essential in modern VLSI design for ensuring manufacturability and achieving high fault coverage. Learners will study fundamental concepts such as Automatic Test Pattern Generation (ATPG), fault models (stuck-at, transition, bridging), scan chain insertion, test compression, boundary scan (IEEE 1149.1), and test coverage analysis. The course integrates both theoretical foundations and hands-on practice, allowing students to implement and verify test structures through lab-based exercises. By the end of the course, learners will be equipped with the knowledge and skills to design circuits for testability, evaluate coverage metrics, and apply industry-standard DFT methodologies to practical silicon design challenges.

This course offers an in-depth exploration of SystemVerilog (SV) for both RTL design and functional verification, building a strong link between hardware description and validation. The course begins with RTL design using SystemVerilog, emphasizing synthesizable constructs, hierarchical design, and best practices for writing modular and reusable code. It then shifts focus to SystemVerilog as a Hardware Verification Language (HVL), introducing advanced verification techniques such as object-oriented programming, constrained randomization, and functional coverage. Learners will also gain proficiency in writing SystemVerilog Assertions (SVA) for property checking and applying formal verification to ensure design correctness early in the development cycle. Combining theoretical insights with hands-on practice, this course equips students with the ability to design reliable hardware and build efficient, assertion-based verification environments.

This course lays the foundation for developing and debugging modern embedded systems. The course begins with hardware system interfacing fundamentals and introduces learners to microprocessors and microcontrollers, with platforms such as STMicroelectronics serving as examples. Emphasis is placed on embedded C programming for system-level applications. Learners also gain exposure to the ARM Instruction Set Architecture (ISA) and supporting toolchains, while exploring key quality attributes of embedded systems. Additionally, the course introduces debug interfaces and debuggers such as SWD and JTAG, providing practical insight into low-level programming, system control, and debugging practices essential for embedded system development.

This course builds on foundational concepts to provide learners with a comprehensive understanding of embedded peripheral interfaces from a programmer’s perspective. The course explores the internal functionality and software-level integration of analog and digital peripherals, such as ADCs, DACs, sensors, buttons, LEDs, LCDs, and other input/output devices, using microcontroller platforms. Learners will gain practical experience in controlling and interfacing peripherals through embedded programming.

In addition, the course introduces the fundamentals of embedded networking, covering widely used communication stacks and protocols including TCP/IP and UDP. Emphasis is placed on the layered architecture of networking stacks, packet structures, socket programming, and applications in IoT and embedded systems. Through applied programming exercises and lab-based activities, learners will acquire hands-on skills in peripheral integration and implementing network communication protocols for real-world embedded applications.

This course offers immersive, project-based practice in VLSI and embedded systems, allowing students to translate theoretical knowledge into real-world design and verification tasks. Learners gain proficiency with industry-standard tools, scripting workflows, and complete design methodologies. By engaging with practical exercises across multiple domains, students build the applied expertise and confidence required for careers in the semiconductor and embedded systems industries.

This course offers a comprehensive study of Physical Synthesis and Physical Design in the VLSI implementation flow, emphasizing the transformation of synthesized RTL into optimized and manufacturable layouts. Students will explore timing-driven placement, logic restructuring, and multi-objective optimization for area, power, and performance. The course further examines the complete Physical Design flow, covering floorplanning, placement, clock tree synthesis (CTS), routing, and signoff checks such as timing analysis. Through practical labs and industry-standard tool exercises, learners will develop the ability to perform both block-level and full-chip physical design, ensuring compliance with stringent fabrication and performance requirements.

This course provides an applied, integrative experience across semiconductor and embedded system design, bridging theory with real-world practice. Students engage in structured projects that involve design tool flows, scripting, verification, and testing strategies. Working through sub-block or full-chip development cycles with guided mentorship, learners participate in milestone-based reviews and collaborative problem-solving. This experience cultivates a comprehensive understanding of how multiple disciplines converge in chip design and production, preparing students for professional engineering environments.

This course introduces learners to the architecture, design methodologies, and communication protocols central to modern System-on-Chip (SoC) development. The course begins with a detailed study of SoC architecture, emphasizing the integration of processing cores, memory subsystems, and hardware accelerators. Learners will gain an understanding of the complete SoC design flow, including specification, IP integration, simulation, synthesis, verification, and physical design. The course highlights interconnect protocols such as AXI, AHB, and APB, exploring how bridges and bus fabrics enable seamless communication between IP blocks. Additionally, students will examine processor–peripheral communication through protocols like I²C, SPI, UART, and GPIO, while also being introduced to wireless communication standards such as Wi-Fi and Bluetooth. Special focus is placed on their architectures, stack layers, and the integration challenges encountered in SoC design.

This course provides an in-depth exploration of essential infrastructure components and software foundations in modern System-on-Chip (SoC) design. The course begins with a detailed study of memories and memory controllers, covering SRAM, DRAM, and Flash, along with interfacing methods and controller architectures designed to optimize latency, bandwidth, and power consumption. Learners will then examine Memory Management Units (MMUs) and virtual memory mechanisms such as address translation, paging, segmentation, and protection, which are integral to contemporary processor architectures. The course also focuses on interrupt controllers, exploring interrupt types, prioritization, masking, nested interrupts, and their integration with CPU cores to ensure responsive system performance. A dedicated section addresses SoC system controllers, including subsystems for clock and reset management, timers, power management units (PMUs), and pin multiplexing. Finally, the course introduces the SoC software stack, encompassing operating systems, firmware, device drivers, communication stacks, applications, and development toolchains. Through this, learners gain insights into the interplay between hardware and software, and how abstraction layers like firmware and drivers manage hardware resources effectively. ​​The module extends system-on-chip design concepts to include hardware virtualisation support and AI-oriented accelerator integration. Students examine virtualised SoC interconnects, NPU dataflows, and RISC-V vector capabilities within modern heterogeneous SoC architectures.

This course** provides learners with the foundational knowledge and applied skills essential for careers in the semiconductor and embedded systems industry. The course integrates theoretical concepts with practical implementation, covering both front-end and back-end VLSI design methodologies. Learners are introduced to VLSI design principles, ASIC and FPGA workflows, and industry-standard verification processes. Building on digital logic fundamentals, the course incorporates the RISC-V Instruction Set Architecture, guiding students toward the Register Transfer Level (RTL) design and implementation of a pipelined RISC-V processor. In addition, learners explore CMOS basics, full-custom ASIC design strategies, and critical timing concepts. By connecting digital electronics theory with practical applications, the course enables students to design systems that are functionally correct, synthesizable, and optimized for performance and resource efficiency.

This course provides a structured introduction to the Verilog Hardware Description Language (HDL), equipping learners with the ability to model, simulate, and design digital systems at the RTL level. The course begins with the fundamentals of Verilog, including modules, data types, procedural and continuous assignments, as well as behavioral and structural modeling. Learners will gain practical experience in hardware design environments through the use of Linux commands and the VI editor. Building on this foundation, the course advances to complex Verilog concepts such as tasks, functions, synthesizable constructs, and testbench development, with a strong emphasis on writing modular, reusable, and efficient code. Finally, learners are introduced to code coverage techniques, enabling them to evaluate verification quality and completeness effectively.